718 offres d'emploi DIGITAL IC VERIFICATION ENGINEER - |
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Lieu : Leuven Flanders Société : ICsense NV design and verification of high-quality digital and mixed-signal ICsWrite digital specifications for mixed-signal ICs,..
Postuler | Plus d'offres Senior Digital Design Engineer Plus d'offres - Leuven |
Lieu : Leuven Flanders Société : ICsense NV constrained randomized tests and to gather and interpret metrics such as code/condition/FSM/toggle/functional coverageYou have experience with digital synthesis,..
Postuler | Plus d'offres Senior Digital Design Engineer Plus d'offres - Leuven |
Lieu : Leuven Flanders Société : ICsense NV design and verification of high quality ICs,..design and verification of high-quality digital and mixed-signal ICsWrite digital specifications for mixed-signal ICs,..
Postuler | Plus d'offres Senior Digital Design Engineer Plus d'offres - Leuven |
Lieu : Leuven Flanders Société : Cyient selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Engineering6+ years of relevant digital design experienceStrong communication,..
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Lieu : Leuven Flanders Société : Cyient ..formal verification,..Memory and Peripheral SubsystemsPreferred QualificationKnowledge of mixed signal conceptsFunctional Verification experience or understanding (assertion based verification,..
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Lieu : Leuven Flanders Société : Cyient formal verification,..& Power OptimizationCollaboration with verification team on planning and execution,..
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Lieu : Leuven Flanders Société : Cyient As part of our Digital Design team,..selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Engineering6+ years of relevant digital<..
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Lieu : Leuven Flanders Société : Cyient & Power OptimizationCollaboration with verification team on planning and execution,..Memory and Peripheral SubsystemsPreferred QualificationKnowledge of mixed signal conceptsFunctional Verification experience or understanding (assertion based verification,..
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Lieu : Leuven Flanders Société : Cyient ..& Power OptimizationCollaboration with verification team on planning and execution,..Python,..static timing analysis and power analysis)Experience with scripting languages (TCL,..
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Lieu : Leuven Flanders Société : Cyient formal verification,..Memory and Peripheral SubsystemsPreferred QualificationKnowledge of mixed signal conceptsFunctional Verification experience or understanding (assertion based verification,..
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Lieu : Leuven Flanders Société : Cyient & Power OptimizationCollaboration with verification team on planning and execution,..As part of our Digital Design team,..
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Lieu : Leuven Flanders Société : Cyient Memory and Peripheral SubsystemsPreferred QualificationKnowledge of mixed signal conceptsFunctional Verification experience or understanding (assertion based verification,..
Postuler |
Lieu : Leuven Flanders Société : Cyient As part of our Digital Design team,..Memory and Peripheral SubsystemsPreferred QualificationKnowledge of mixed signal conceptsFunctional Verification experience or understanding (assertion based verification,..
Postuler |
Lieu : Leuven Flanders Société : Cyient & Power OptimizationCollaboration with verification team on planning and execution,..formal verification,..
Postuler |
Lieu : Leuven Flanders Société : Cyient & Power OptimizationCollaboration with verification team on planning and execution,..As part of our Digital Design team,..
Postuler |
Lieu : Leuven Flanders Société : Cyient & Power OptimizationCollaboration with verification team on planning and execution,..selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Postuler |
Lieu : Leuven Flanders Société : Cyient As part of our Digital Design team,..& Power OptimizationCollaboration with verification team on planning and execution,..
Postuler |
Lieu : Leuven Flanders Société : Cyient As part of our Digital Design team,..formal verification,..Memory and Peripheral SubsystemsPreferred QualificationKnowledge of mixed signal conceptsFunctional Verification experience or understanding (assertion based verification,..
Postuler |
Lieu : Leuven Flanders Société : Cyient & Power OptimizationCollaboration with verification team on planning and execution,..formal verification,..
Postuler |
Lieu : Leuven Flanders Société : Cyient ..formal verification,..selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Engineering6+ years of relevant digital design ex..
Postuler |
Lieu : Leuven Flanders Société : Cyient As part of our Digital Design team,..& Power OptimizationCollaboration with verification team on planning and execution,..
Postuler |
Lieu : Leuven Flanders Société : Cyient & Power OptimizationCollaboration with verification team on planning and execution,..selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Postuler |
Lieu : Leuven Flanders Société : Cyient & Power OptimizationCollaboration with verification team on planning and execution,..selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Postuler |
Lieu : Leuven Flanders Société : Cyient selection and integrationContribute to flow and methodology developmentThis a position that requires leading a teamMinimum QualificationBachelor’s or Master’s Degree in Electrical or Computer Engineering6+ years of relevant digital design experienceStrong communication,..
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Lieu : Leuven Flanders Société : Cyient you’ll take imaginative ideas and turn them into reality.ResponsibilitiesArchitecture/Micro-architecture specification developmentRTL implementation using VHDL or Verilog/System VerilogLint,..
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